1. Field of the Invention
The present invention generally relates to a process for fabricating capacitor configurations of dynamic random access memory (DRAM) devices. In particular, the present invention relates to a process for fabricating capacitor configurations of DRAM devices having increased capacitance thereof.
2. Technical Background
A primary use of capacitors in digital electronic circuitry is to hold binary electronic data. Due to the inevitable leakage in such capacitors, a larger capacitance means a more sustained holding of the data. Capacitor configurations having larger electrode surface area will have a relatively greater electrical capacitance because capacitance is directly proportional to the effective electrode surface area.
Unfortunately, enlarging the electrode surface area is contrary to the trend of reducing physical device dimensions. It is therefore inherently difficult to reduce the physical dimensions of the device while simultaneously maximizing the capacitor electrode surface area. In the past such efforts usually resulted in complicated fabrication procedures that suffer from low yield rates due to high reject rates.
A review of the conventional capacitor configuration for a typical DRAM device of the stacked capacitor configuration, such as that depicted in FIG. 1 of the drawing, will demonstrate this fabrication difficulty. As is seen in FIG. 1, the capacitor is fabricated over the silicon semiconductor substrate 10. A field oxide layer 11 is formed first, followed by the formation of the gate configuration 12 as well as the source/drain regions 18 to constitute the transistor element for the memory cell of the fabricated DRAM device. An oxide layer 13 is then formed over the surface of the transistor configuration, with a contact opening etched out of the oxide layer 13 over the designated area of the source/drain regions 18. A polysilicon layer 14 is next formed over the contact opening, followed by the formation of a dielectric layer 15 having a structural configuration such as, for example, an NO (nitride/oxide) or an ONO (oxide/nitride/oxide) configuration. A second polysilicon layer 16 is subsequently formed over the surface of the dielectric layer 15. This constitutes the capacitor configuration for the memory cell unit of the DRAM device. Finally, a metal configuration 17 is formed, along with the isolation layers not shown in the drawing, to generally conclude the fabrication of the integrated circuit device.
Such prior art memory cell unit construction with its incorporated capacitor configuration is limited in the capacitance it can provide, especially as memory devices such as DRAM's must be kept dimensionally small. As capacitance is inherently proportional to the surface area of the capacitor configuration, there is a drastic decrease in capacitance when the memory cell unit dimensions are reduced for the purpose of packing more memory capacity into the memory device.
Two basic approaches are apparent for increasing the capacitor capacitance in the fabrication of such memory devices. One approach is to reduce the thickness of the dielectric layer 15 sandwiched between the electrodes. The very thin dielectric layer 15 enhances the electric field intensity between the electrodes, namely the first and second polysilicon layers 14 and 16 separated by the dielectric layer 15 itself, thereby effectively increasing the amount of electrical charge that may be held between the electrodes.
However, this approach has its limitations. Direct carrier tunneling effect may result if the thickness of the dielectric layer 15 falls below less than 50 angstrom. Direct carrier tunneling causes excessive current leakage between electrode layers 14 and 16.
The other approach is to construct capacitors having a trenched configuration. Deep trenches are by etched into the lateral sides of the transistor units formed on the silicon substrate. These trenches constitute the curved surface of capacitor electrodes, thereby expanding the overall surface area of the capacitor configuration thus constructed. However, the formation of deep trenches is difficult. As the etching aspect ratio increases, the time required for etching becomes excessively long and there is further the inevitable side effect of an increased defect rate which increases current leakage in the capacitor.
Improved, stacked capacitor configurations have also been proposed which employ improved morphology for the electrode surfaces of the capacitor configuration. The resultant non-uniform surface of the capacitor electrodes expands the effective surface area of the capacitor, thereby increasing its effective capacitance. Several previously proposed improved stacked capacitor configurations are shown in FIGS. 2, 3 and 4. In these drawing figures, reference numerals 14, 15 and 16 designate the first polysilicon layer, the dielectric layer, and the second polysilicon layer, respectively, of the capacitor configuration.
In general, when compared with the structural capacitor configuration of FIG. 1, the configurations shown in FIGS. 2, 3 and 4 have an increased capacitor electrode surface area for an enhanced capacitance. However, the extent to which the capacitance can be increased is limited to about three-fold, which is insufficient for and incompatible with the required degree of device dimension reduction. Furthermore, these capacitor configurations, as mentioned above, require complicated and difficult fabrication procedures.